In the production of MOSFET structures, especially within the framework of a CMOS process, so-called LDD regions (lightly doped drain) are formed on the source side and the drain side of the channel for the purpose of improving the functional performance of the transistor. This measure serves to reduce short channel effects, especially DIBL, punch-through, GIDL and Vt roll-off, for example. The LDD regions are formed between the source region and the channel region, and between the channel region and the drain region. They reduce the otherwise very high electric field intensities between the source region and/or drain region and the channel region.
In the production of complementary transistors within the framework of a CMOS process, the transistors intended as a first type are masked. The remaining transistors then undergo an implantation of low-dose dopant, in order to produce the LDD regions. The mask is removed, and the transistors that were previously implanted are shielded using another mask. This is followed by an implantation of dopant of the opposite conductivity type, whereby the LDD regions of the complementary transistors are produced. In order to adequately offset the source regions and drain regions, which will subsequently be implanted, from the channel regions, and thereby to suppress a potential punch-through, reduce the GIDL effect and minimize a degradation of the MOSFET by hot carrier effects, sidewall spacers are set up on the source-side and drain-side sidewalls of the gate electrodes. In order to allow the implantation of the dopant for the source regions and drain regions at a higher dopant concentration, two additional masks must then be used to cover the transistors of both types. This requires a total of four masks. Due to the benefits that have been realized through LDD regions, other such structures have been developed and studied, such as LATID (large-angle tilted implant drain) and DDD, for example.